1. Field of the Invention
The present invention relates to cache logic for a data processing apparatus, a data processing apparatus including such cache logic, and a method of operating the cache logic.
2. Description of the Prior Art
A data processing apparatus will typically include one or more data processing units which are operable to perform data processing operations on data values stored in memory. Since accesses to memory are relatively slow, and hence are likely to adversely impact the performance of the processing unit, it is known to provide one or more caches within the data processing apparatus for storing a subset of the data values so that they can be made available to the processing unit more quickly than if instead they had to be accessed directly from memory.
When a processing unit wishes to access a data value, it will typically issue an access request specifying an address in memory of the data value required to be accessed. A cache receiving that access request will typically be arranged to determine from the specified address, or at least from a portion thereof, whether the data value the subject of the access request is stored within one of the cache lines of the cache (this being referred to as a hit condition), and if so to allow the data value to be accessed in the cache. For a write access, this will involve updating the relevant data value within the identified cache line, whereas for a read access this will involve returning to the processing unit the data value as read from the identified cache line.
Some regions of memory can be specified as write through regions, and if a write access request is issued in respect of a data value within a write through region of memory, and that data value is found to exist within the cache, the data value is updated in the cache and at the same time is updated in memory, as a result of which the contents in the cache remain coherent with the contents in memory.
However, it is also possible to specify regions of memory as write back regions, and in the event of a write access request being issued in respect of a data value within a write back region of memory, if that data value is found within the cache, it is updated within the cache without the need at the same time to propagate the update to memory. Instead, typically the cache line containing that updated data value is marked as dirty, so that the updated data value can be stored to memory if that cache line is subsequently evicted from the cache.
If on receipt of an access request, the cache determines that the data value the subject of the access request is not present in the cache (referred to as a miss condition), then the cache may be arranged to perform a linefill operation in order to retrieve into the cache a cache line's worth of data from memory, including the data value the subject of the access request, so that the data value can then be accessed directly from the cache. As part of such a linefill procedure, it will typically be necessary to select a cache line to be evicted from the cache in order to make space for the new content being retrieved from memory. There are many known replacement policies for deciding on a suitable cache line to evict and once a cache line is selected as an evicted cache line, its current contents are output to memory and the cache line marked as invalid. Once the current content has been evicted, a linefill can take place, this typically involving a linefill request being issued to external memory, and then when the new content is returned from the external memory, that new content is written to the evicted cache line and the cache line is marked as valid.
There is often a significant period of time between output of the current content of an evicted line and the marking of that evicted cache line as invalid, and the availability of the new content for storing in that evicted cache line.
During that period of time, it is not unusual to observe the processing unit issuing a subsequent access request seeking to access a data value within the current content of the evicted line. However, when evicting the current content, the cache line was marked as invalid, and accordingly it is not possible for the processing unit to access that cache line. Instead, the processing unit has to wait until the eviction of the current content of the evicted cache line has finished (i.e. the memory has successfully received and stored that content), and thereafter needs to initiate a new linefill operation in order to obtain that data back from memory.
This can give rise to a significant impact on performance.